The microelectronic industry is continually striving to produce ever faster, smaller, and thinner microelectronic packages for use in various electronic products, including, but not limited to, computer server products and portable products, such as wearable microelectronic systems, portable computers, electronic tablets, cellular phones, digital cameras, and the like.
One way to achieve these goals is by increasing integration density, such as by stacking components within the microelectronic package. One stacking method may comprise a method typically used in NAND memory die stacking, wherein a plurality of wirebond pads are formed along one edge of each of the NAND memory dice. The NAND memory dice are stacked on a microelectronic substrate in a staggered or zig-zag configuration to allow access to the wirebond pads. Bond wires are then used to form electrical connections between the wirebond pads on various NAND memory dice and/or between the NAND memory dice and the microelectronic substrate. Although this stacking method allows for flexibility and choice in wirebond pad location, the longest distance for a transmission line to a corresponding wirebond pad location within each NAND memory die may be the entire length of the NAND memory die. This may result in signal degradation due to impedance.
Another stacking method may comprise the use of through-silicon vias wherein signal lines are formed in and through the stacked NAND memory dice to form connections therebetween, as will be understood to those skilled in the art. Through-silicon vias allow for very short conductor paths between the NAND memory dice and the microelectronic substrate, and longest distance for a transmission line to a corresponding wirebond pad location within each NAND memory die may be a fraction of the length of the NAND memory die. However, the use of through-silicon vias requires an increased number of expensive wafer level processing steps, and may cause reliability issues from copper processing temperature, volume expansion during annealing, and ion migration. Further, the use of through-silicon vias does not allow for flexibility in the positioning of the through-silicon vias within the individual microelectronic dice, as the connection must be made straight down through the microelectronic die stack.
Therefore, there is a need to develop novel microelectronic die stacking configurations and designs to reduce signal transmission lengths, minimize costs, and improve reliability.